Computers are continually progressing in several key areas, including speed of operation and peripheral device support. However, progression in some areas can often impede progression in other areas. For example, to many conventional computers utilize a cache memory system for storing one or more duplicate memory portions of a computer's main memory. The cache thereby allows a device such as a central processing unit ("CPU") to make multiple, quick accesses to a localized area of the main memory. Typically, a cache has relatively fast access times for read and write operations being performed by the CPU, as compared to the main memory, but the cache is more expensive than the main memory. Therefore, a balance must be struck between the size of the cache relative to the main memory of the computer.
The cache is typically organized in cache lines, which are groupings of data words. For example, a cache line may consist of sixteen data words. Also, read and write operations to the cache are focused on one entire cache line at a time. Read operations are fairly straightforward, but write operations can present several difficulties. One difficulty revolves around what to do with stale main memory. A stale main memory occurs when a write operation has been performed on the cache so that the cache no longer duplicates, or is no longer coherent with, the corresponding portion of main memory. To resolve this difficulty, several types of caches have been commonly implemented, two types being "write back" and "write through". Each of the two cache types has benefits and drawbacks well known by those of ordinary skill in the art.
In addition to the CPU, the cache, and the main memory, a computer supports a variety of peripheral devices. The peripheral devices are typically connected to each other through a peripheral bus and interface the CPU, cache and main memory through a bridge device. Due to the operation of the peripheral devices, implementation of the write back cache presents additional difficulties. This is because the peripheral devices request read operations to portions of the computer's main memory which are frequently stale. As a result, when a peripheral device has control of the peripheral bus and begins to perform a memory read operation, i.e., the peripheral device becomes a bus mastering agent, a determination must first be made as to whether the requested portion of the main memory needs to be updated by the cache. Therefore, a snoop operation is typically employed to determine the state of the requested portion of main memory in the cache.
Since both the CPU and the peripheral devices are accessing the computer's main memory and the cache, the slave device should support quick operation of the CPU as well as adequate support of the peripheral devices. To provide such support, the slave device often utilizes one or more memory management techniques. For example, the slave device may utilize look-ahead, or "speculative", techniques for increasing the bandwidth, or rate of data transfer, from memory to the CPU or the bus mastering agent. It is understood that a variety of speculative techniques are well known in the art.
Despite the improvements provided by the use of such speculative techniques, there are certain instances when a single bus mastering agent attempts to monopolize the bus. One such instance is when the bus mastering agent requests a misaligned memory read operation. A misaligned memory read operation is a memory access to a location that does not begin at the beginning of a cache line. In the example above where one cache line is sixteen data words long, a misaligned memory read operation may attempt to read data beginning with the fourth data word of the cache line.
To prevent a bus mastering agent from monopolizing the bus, the slave may utilize a monitored latency period. A monitored latency period is a limit on how long a single bus mastering agent can own or control the bus. Once that limit has been reached, the bus mastering agent is preempted, thereby terminating its ownership of the bus. While this technique prevents monopolization of the bus by a single bus mastering agent, it sometimes has an overall effect of slowing down the computer because the bus mastering agent must again arbitrate for ownership of the bus to finish its request. Furthermore, when speculative read techniques are employed, in conjunction with the monitored latency period, the benefits of the speculative read are somewhat diminished in situations where the data is cached but the bus mastering agent is preempted.